Index: gpu/ipc/client/gpu_channel_host.h |
diff --git a/gpu/ipc/client/gpu_channel_host.h b/gpu/ipc/client/gpu_channel_host.h |
index 5acf6c79a5fdbcf4d917dd6967b2e9b1336f789e..b394d755d522569a215704c29ffa7ed54d7094a6 100644 |
--- a/gpu/ipc/client/gpu_channel_host.h |
+++ b/gpu/ipc/client/gpu_channel_host.h |
@@ -27,6 +27,7 @@ |
#include "ipc/message_filter.h" |
#include "ipc/message_router.h" |
#include "ui/events/latency_info.h" |
+#include "ui/gfx/gpu_fence.h" |
#include "ui/gfx/gpu_memory_buffer.h" |
namespace base { |
@@ -154,6 +155,15 @@ class GPU_EXPORT GpuChannelHost |
// Reserve one unused image ID. |
int32_t ReserveImageId(); |
+ // Returns a GPU fence handle to the fence that can be sent via |
+ // IPC to the GPU process. The caller is responsible for ensuring it is |
+ // closed. Returns an invalid handle on failure. |
+ gfx::GpuFenceHandle ShareGpuFenceToGpuProcess( |
+ const gfx::GpuFenceHandle& source_handle); |
+ |
+ // Reserve one unused fence ID. |
+ int32_t ReserveFenceId(); |
+ |
// Generate a route ID guaranteed to be unique for this channel. |
int32_t GenerateRouteID(); |
@@ -273,6 +283,9 @@ class GPU_EXPORT GpuChannelHost |
// Image IDs are allocated in sequence. |
base::AtomicSequenceNumber next_image_id_; |
+ // Fence IDs are allocated in sequence. |
+ base::AtomicSequenceNumber next_fence_id_; |
+ |
// Route IDs are allocated in sequence. |
base::AtomicSequenceNumber next_route_id_; |