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Side by Side Diff: src/mips64/constants-mips64.cc

Issue 2375673002: MIPS64: Improve performance of simulator in debug mode. (Closed)
Patch Set: Created 4 years, 2 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #if V8_TARGET_ARCH_MIPS64 5 #if V8_TARGET_ARCH_MIPS64
6 6
7 #include "src/mips64/constants-mips64.h" 7 #include "src/mips64/constants-mips64.h"
8 8
9 namespace v8 { 9 namespace v8 {
10 namespace internal { 10 namespace internal {
(...skipping 103 matching lines...) Expand 10 before | Expand all | Expand 10 after
114 while (aliases_[i].creg != kInvalidRegister) { 114 while (aliases_[i].creg != kInvalidRegister) {
115 if (strcmp(aliases_[i].name, name) == 0) { 115 if (strcmp(aliases_[i].name, name) == 0) {
116 return aliases_[i].creg; 116 return aliases_[i].creg;
117 } 117 }
118 i++; 118 i++;
119 } 119 }
120 120
121 // No Cregister with the reguested name found. 121 // No Cregister with the reguested name found.
122 return kInvalidFPURegister; 122 return kInvalidFPURegister;
123 } 123 }
124
125
126 // -----------------------------------------------------------------------------
127 // Instructions.
128
129 bool Instruction::IsForbiddenAfterBranchInstr(Instr instr) {
130 Opcode opcode = static_cast<Opcode>(instr & kOpcodeMask);
131 switch (opcode) {
132 case J:
133 case JAL:
134 case BEQ:
135 case BNE:
136 case BLEZ: // POP06 bgeuc/bleuc, blezalc, bgezalc
137 case BGTZ: // POP07 bltuc/bgtuc, bgtzalc, bltzalc
138 case BEQL:
139 case BNEL:
140 case BLEZL: // POP26 bgezc, blezc, bgec/blec
141 case BGTZL: // POP27 bgtzc, bltzc, bltc/bgtc
142 case BC:
143 case BALC:
144 case POP10: // beqzalc, bovc, beqc
145 case POP30: // bnezalc, bnvc, bnec
146 case POP66: // beqzc, jic
147 case POP76: // bnezc, jialc
148 return true;
149 case REGIMM:
150 switch (instr & kRtFieldMask) {
151 case BLTZ:
152 case BGEZ:
153 case BLTZAL:
154 case BGEZAL:
155 return true;
156 default:
157 return false;
158 }
159 break;
160 case SPECIAL:
161 switch (instr & kFunctionFieldMask) {
162 case JR:
163 case JALR:
164 return true;
165 default:
166 return false;
167 }
168 break;
169 case COP1:
170 switch (instr & kRsFieldMask) {
171 case BC1:
172 case BC1EQZ:
173 case BC1NEZ:
174 return true;
175 break;
176 default:
177 return false;
178 }
179 break;
180 default:
181 return false;
182 }
183 }
184
185
186 bool Instruction::IsLinkingInstruction() const {
187 switch (OpcodeFieldRaw()) {
188 case JAL:
189 return true;
190 case POP76:
191 if (RsFieldRawNoAssert() == JIALC)
192 return true; // JIALC
193 else
194 return false; // BNEZC
195 case REGIMM:
196 switch (RtFieldRaw()) {
197 case BGEZAL:
198 case BLTZAL:
199 return true;
200 default:
201 return false;
202 }
203 case SPECIAL:
204 switch (FunctionFieldRaw()) {
205 case JALR:
206 return true;
207 default:
208 return false;
209 }
210 default:
211 return false;
212 }
213 }
214
215
216 bool Instruction::IsTrap() const {
217 if (OpcodeFieldRaw() != SPECIAL) {
218 return false;
219 } else {
220 switch (FunctionFieldRaw()) {
221 case BREAK:
222 case TGE:
223 case TGEU:
224 case TLT:
225 case TLTU:
226 case TEQ:
227 case TNE:
228 return true;
229 default:
230 return false;
231 }
232 }
233 }
234
235
236 } // namespace internal 124 } // namespace internal
237 } // namespace v8 125 } // namespace v8
238 126
239 #endif // V8_TARGET_ARCH_MIPS64 127 #endif // V8_TARGET_ARCH_MIPS64
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