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Side by Side Diff: dl/sp/src/arm/arm64/armSP_FFT_CToC_FC32_Radix8_fs_s.S

Issue 1420973006: arm64: clang assembler compatability (Closed) Base URL: https://chromium.googlesource.com/external/webrtc/deps/third_party/openmax@master
Patch Set: arm64: clang assembler compatibility Created 5 years, 1 month ago
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1 // 1 //
2 // Copyright (c) 2013 The WebRTC project authors. All Rights Reserved. 2 // Copyright (c) 2013 The WebRTC project authors. All Rights Reserved.
3 // 3 //
4 // Use of this source code is governed by a BSD-style license 4 // Use of this source code is governed by a BSD-style license
5 // that can be found in the LICENSE file in the root of the source 5 // that can be found in the LICENSE file in the root of the source
6 // tree. An additional intellectual property rights grant can be found 6 // tree. An additional intellectual property rights grant can be found
7 // in the file PATENTS. All contributing project authors may 7 // in the file PATENTS. All contributing project authors may
8 // be found in the AUTHORS file in the root of the source tree. 8 // be found in the AUTHORS file in the root of the source tree.
9 // 9 //
10 // This is a modification of armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.s 10 // This is a modification of armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.s
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345 fadd dVi5,dUi3,dUr7 345 fadd dVi5,dUi3,dUr7
346 fadd dVr7,dUr3,dUi7 346 fadd dVr7,dUr3,dUi7
347 ld2 {dXr3,dXi3},[pSrc],pointStep // data[3] 347 ld2 {dXr3,dXi3},[pSrc],pointStep // data[3]
348 fsub dVi7,dUi3,dUr7 348 fsub dVi7,dUi3,dUr7
349 349
350 // finish third stage of 8 point FFT 350 // finish third stage of 8 point FFT
351 351
352 .ifeqs "\inverse", "TRUE" 352 .ifeqs "\inverse", "TRUE"
353 353
354 // calculate a*v5 354 // calculate a*v5
355 fmul dT1,dVr5,dT0[0] // use dVi0 for dT1 355 fmul dT1,dVr5,dT0s[0] // use dVi0 for dT1
356 356
357 ld2 {dXr4,dXi4},[pSrc],pointStep // data[4] 357 ld2 {dXr4,dXi4},[pSrc],pointStep // data[4]
358 fmul dVi5,dVi5,dT0[0] 358 fmul dVi5,dVi5,dT0s[0]
359 359
360 ld2 {dXr5,dXi5},[pSrc],pointStep // data[5] 360 ld2 {dXr5,dXi5},[pSrc],pointStep // data[5]
361 fsub dVr5,dT1,dVi5 // a * V5 361 fsub dVr5,dT1,dVi5 // a * V5
362 fadd dVi5,dT1,dVi5 362 fadd dVi5,dT1,dVi5
363 363
364 ld2 {dXr6,dXi6},[pSrc],pointStep // data[6] 364 ld2 {dXr6,dXi6},[pSrc],pointStep // data[6]
365 365
366 // calculate b*v7 366 // calculate b*v7
367 fmul dT1,dVr7,dT0[0] 367 fmul dT1,dVr7,dT0s[0]
368 fmul dVi7,dVi7,dT0[0] 368 fmul dVi7,dVi7,dT0s[0]
369 369
370 // fadd qY1,qV1,qV5 370 // fadd qY1,qV1,qV5
371 // fsub qY5,qV1,qV5 371 // fsub qY5,qV1,qV5
372 fadd dYr1,dVr1,dVr5 372 fadd dYr1,dVr1,dVr5
373 fsub dYr5,dVr1,dVr5 373 fsub dYr5,dVr1,dVr5
374 fadd dYi1,dVi1,dVi5 374 fadd dYi1,dVi1,dVi5
375 fsub dYi5,dVi1,dVi5 375 fsub dYi5,dVi1,dVi5
376 376
377 fadd dVr7,dT1,dVi7 // b * V7 377 fadd dVr7,dT1,dVi7 // b * V7
378 fsub dVi7,dVi7,dT1 378 fsub dVi7,dVi7,dT1
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392 392
393 393
394 st2 {dYr3,dYi3},[pDst],step1 // store y3 394 st2 {dYr3,dYi3},[pDst],step1 // store y3
395 st2 {dYr5,dYi5},[pDst],step1 // store y5 395 st2 {dYr5,dYi5},[pDst],step1 // store y5
396 st2 {dYr7,dYi7},[pDst] // store y7 396 st2 {dYr7,dYi7},[pDst] // store y7
397 ADD pDst, pDst, #16 397 ADD pDst, pDst, #16
398 398
399 .else 399 .else
400 400
401 // calculate b*v7 401 // calculate b*v7
402 fmul dT1,dVr7,dT0[0] 402 fmul dT1,dVr7,dT0s[0]
403 ld2 {dXr4,dXi4},[pSrc],pointStep // data[4] 403 ld2 {dXr4,dXi4},[pSrc],pointStep // data[4]
404 fmul dVi7,dVi7,dT0[0] 404 fmul dVi7,dVi7,dT0s[0]
405 405
406 ld2 {dXr5,dXi5},[pSrc],pointStep // data[5] 406 ld2 {dXr5,dXi5},[pSrc],pointStep // data[5]
407 fadd dVr7,dT1,dVi7 // b * V7 407 fadd dVr7,dT1,dVi7 // b * V7
408 fsub dVi7,dVi7,dT1 408 fsub dVi7,dVi7,dT1
409 409
410 ld2 {dXr6,dXi6},[pSrc],pointStep // data[6] 410 ld2 {dXr6,dXi6},[pSrc],pointStep // data[6]
411 411
412 // calculate a*v5 412 // calculate a*v5
413 fmul dT1,dVr5,dT0[0] // use dVi0 for dT1 413 fmul dT1,dVr5,dT0s[0] // use dVi0 for dT1
414 fmul dVi5,dVi5,dT0[0] 414 fmul dVi5,dVi5,dT0s[0]
415 415
416 fadd dYr7,dVr3,dVr7 416 fadd dYr7,dVr3,dVr7
417 fadd dYi7,dVi3,dVi7 417 fadd dYi7,dVi3,dVi7
418 SUB pDst, pDst, step2 // set pDst to y1 418 SUB pDst, pDst, step2 // set pDst to y1
419 419
420 fsub dVr5,dT1,dVi5 // a * V5 420 fsub dVr5,dT1,dVi5 // a * V5
421 fadd dVi5,dT1,dVi5 421 fadd dVi5,dT1,dVi5
422 422
423 // On the last iteration, this will read past the end of pSrc, 423 // On the last iteration, this will read past the end of pSrc,
424 // so skip this read. 424 // so skip this read.
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464 M_END 464 M_END
465 465
466 466
467 M_START armSP_FFTInv_CToC_FC32_Radix8_fs_OutOfPlace,,d15 467 M_START armSP_FFTInv_CToC_FC32_Radix8_fs_OutOfPlace,,d15
468 FFTSTAGE "FALSE","TRUE",INV 468 FFTSTAGE "FALSE","TRUE",INV
469 M_END 469 M_END
470 470
471 471
472 472
473 .end 473 .end
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