arm64: clang assembler compatability

dl/sp/src/arm/arm64/ComplexToRealFixup.S

 //
 //  Copyright (c) 2013 The WebRTC project authors. All Rights Reserved.
 //
 //  Use of this source code is governed by a BSD-style license
 //  that can be found in the LICENSE file in the root of the source
 //  tree. An additional intellectual property rights grant can be found
 //  in the file PATENTS.  All contributing project authors may
 //  be found in the AUTHORS file in the root of the source tree.
 //
 //  This is a modification of omxSP_FFTFwd_RToCCS_S32_Sfs_s.s
@@ skipping 76 matching lines @@
 #define dW1r8b    v16.8b
 #define dW1i      v17.2s
 #define dY0r      v14.2s
 #define dY0i      v15.2s
 #define dY1r      v16.2s
 #define dY1i      v17.2s
 #define qT2       v18.2s
 #define qT3       v20.2s
 
 #define half      v0.2s
+#define halfs     v0.s
 #define dZip      v21.2s
 #define dZip8b    v21.8b
         
     // Allocate stack memory required by the function
 
     // Write function header
         M_START     ComplexToRealFixup,,d15
 
         asr     N, N, #1
 
         clz     order, subFFTNum                    // N = 2^order
 
-        RSB     order,order,#63
+        rsb     order,order,#63
         MOV     subFFTSize,subFFTNum            // subFFTSize = N/2
         //MOV     subFFTNum,N
         mov     argDst, pDst
         mov     argTwiddle, pTwiddle
 
         // F(0) = 1/2[Z(0) + Z'(0)] - j [Z(0) - Z'(0)]
         // 1/2[(a+jb) + (a-jb)] - j  [(a+jb) - (a-jb)]
         // 1/2[2a+j0] - j [0+j2b]
         // (a+b, 0)
 
         // F(N/2) = 1/2[Z(0) + Z'(0)] + j [Z(0) - Z'(0)]
         // 1/2[(a+jb) + (a-jb)] + j  [(a+jb) - (a-jb)]
         // 1/2[2a+j0] + j [0+j2b]
         // (a-b, 0)
 
         // F(0) and F(N/2)
         ld2     {dX0rs,dX0is}[0],[pSrc], #8
         MOV     zero,#0
         mov    dX0rs[1],zero
         lsl     step,subFFTSize, #3               // step = N/2 * 8 bytes
-        mov    dX0i[1],zero
+        mov    dX0is[1],zero
         // twStep = 3N/8 * 8 bytes pointing to W^1
         SUB     twStep,step,subFFTSize,LSL #1
 
         fadd    dY0r,dX0r,dX0i                    // F(0) = ((Z0.r+Z0.i) , 0)
         lsl     step1,subFFTSize, #2              // step1 = N/2 * 4 bytes
         fsub    dY0i,dX0r,dX0i                    // F(N/2) = ((Z0.r-Z0.i) , 0)
         SUBS    subFFTSize,subFFTSize,#2
 
         st1     {dY0r},[argDst],step
         ADD     pTwiddleTmp,argTwiddle,#8         // W^2
@@ skipping 37 matching lines @@
         rev64   dX1i,dX1i
         SUBS    subFFTSize,subFFTSize,#4
 
 
 
         fsub    dT2,dX0r,dX1r                     // a-c
         SUB     step1,step1,#8
         fadd    dT0,dX0r,dX1r                     // a+c
         fsub    dT1,dX0i,dX1i                     // b-d
         fadd    dT3,dX0i,dX1i                     // b+d
-        fmul   dT0,dT0,half[0]
-        fmul   dT1,dT1,half[0]
+        fmul   dT0,dT0,halfs[0]
+        fmul   dT1,dT1,halfs[0]
         // VZIP    dW1r,dW1i
         // VZIP    dW0r,dW0i
         zip1    dZip, dW1r, dW1i
         zip2    dW1i, dW1r, dW1i
         mov     dW1r8b, dZip8b
         zip1    dZip, dW0r, dW0i
         zip2    dW0i, dW0r, dW0i
         mov     dW0r8b, dZip8b
 
         fmul   qT0,dW1r,dT2
         fmul   qT1,dW1r,dT3
         fmul   qT2,dW0r,dT2
         fmul   qT3,dW0r,dT3
 
         fmla   qT0,dW1i,dT3
         fmls   qT1,dW1i,dT2
 
         fmls   qT2,dW0i,dT3
         fmla   qT3,dW0i,dT2
 
 
-        fmul  dX1r,qT0,half[0]
-        fmul  dX1i,qT1,half[0]
+        fmul  dX1r,qT0,halfs[0]
+        fmul  dX1i,qT1,halfs[0]
 
         fsub    dY1r,dT0,dX1i                     // F(N/2 -1)
         fadd    dY1i,dT1,dX1r
         fneg    dY1i,dY1i
 
         rev64   dY1r,dY1r
         rev64   dY1i,dY1i
 
 
-        fmul  dX0r,qT2,half[0]
-        fmul  dX0i,qT3,half[0]
+        fmul  dX0r,qT2,halfs[0]
+        fmul  dX0i,qT3,halfs[0]
 
         fsub    dY0r,dT0,dX0i                     // F(1)
         fadd    dY0i,dT1,dX0r
 
 
         st2     {dY0r,dY0i},[argDst],step
         st2     {dY1r,dY1i},[argDst], #16
         SUB     argDst,argDst,step
         SUB     step,step,#32                     // (N/2-4)*8 bytes
 
@@ skipping 18 matching lines @@
 
         st1     {dX0rs}[0],[argDst], #4
         fneg    dX0r,dX0r
         st1     {dX0rs}[1],[argDst], #4
 End:
 
         // Write function tail
         M_END
 
         .end