arm64: clang assembler compatability

dl/sp/src/arm/arm64/ComplexToRealFixup.S

 //
 //  Copyright (c) 2013 The WebRTC project authors. All Rights Reserved.
 //
 //  Use of this source code is governed by a BSD-style license
 //  that can be found in the LICENSE file in the root of the source
 //  tree. An additional intellectual property rights grant can be found
 //  in the file PATENTS.  All contributing project authors may
 //  be found in the AUTHORS file in the root of the source tree.
 //
 //  This is a modification of omxSP_FFTFwd_RToCCS_S32_Sfs_s.s
@@ skipping 75 matching lines @@
 #define dW1r      v16.2s
 #define dW1r8b    v16.8b
 #define dW1i      v17.2s
 #define dY0r      v14.2s
 #define dY0i      v15.2s
 #define dY1r      v16.2s
 #define dY1i      v17.2s
 #define qT2       v18.2s
 #define qT3       v20.2s
 
-#define half      v0.2s
+#define half      v0.s
 #define dZip      v21.2s
 #define dZip8b    v21.8b
         
     // Allocate stack memory required by the function
 
     // Write function header
         M_START     ComplexToRealFixup,,d15
 
         asr     N, N, #1
 
         clz     order, subFFTNum                    // N = 2^order
 
-        RSB     order,order,#63
+        rsb     order,order,#63
         MOV     subFFTSize,subFFTNum            // subFFTSize = N/2
         //MOV     subFFTNum,N
         mov     argDst, pDst
         mov     argTwiddle, pTwiddle
 
         // F(0) = 1/2[Z(0) + Z'(0)] - j [Z(0) - Z'(0)]
         // 1/2[(a+jb) + (a-jb)] - j  [(a+jb) - (a-jb)]
         // 1/2[2a+j0] - j [0+j2b]
         // (a+b, 0)
 
         // F(N/2) = 1/2[Z(0) + Z'(0)] + j [Z(0) - Z'(0)]
         // 1/2[(a+jb) + (a-jb)] + j  [(a+jb) - (a-jb)]
         // 1/2[2a+j0] + j [0+j2b]
         // (a-b, 0)
 
         // F(0) and F(N/2)
         ld2     {dX0rs,dX0is}[0],[pSrc], #8
         MOV     zero,#0
         mov    dX0rs[1],zero
         lsl     step,subFFTSize, #3               // step = N/2 * 8 bytes
-        mov    dX0i[1],zero
+        mov    dX0is[1],zero
         // twStep = 3N/8 * 8 bytes pointing to W^1
         SUB     twStep,step,subFFTSize,LSL #1
 
         fadd    dY0r,dX0r,dX0i                    // F(0) = ((Z0.r+Z0.i) , 0)
         lsl     step1,subFFTSize, #2              // step1 = N/2 * 4 bytes
         fsub    dY0i,dX0r,dX0i                    // F(N/2) = ((Z0.r-Z0.i) , 0)
         SUBS    subFFTSize,subFFTSize,#2
 
         st1     {dY0r},[argDst],step
         ADD     pTwiddleTmp,argTwiddle,#8         // W^2
         st1     {dY0i},[argDst], #8
         ADD     argTwiddle,argTwiddle,twStep      // W^1
 
 //        dup     dzero,zero
         SUB     argDst,argDst,step
 
         BLT     End
         BEQ     lastElement
         SUB     step,step,#24
         SUB     step1,step1,#8                    // (N/4-1)*8 bytes
 
         // F(k) = 1/2[Z(k) +  Z'(N/2-k)] -j*W^(k) [Z(k) -  Z'(N/2-k)]
         // Note: W^k is stored as negative values in the table
         // Process 4 elements at a time. E.g: F(1),F(2) and F(N/2-2),F(N/2-1)
         // since both of them require Z(1),Z(2) and Z(N/2-2),Z(N/2-1)
 
-        fmov     half, #0.5
+        fmov     v0.2s, #0.5

[Raymond Toy (Google), 2015/10/30 22:38:46]

I think you should change the definition of half instead of using v0.2s here. 
Or something that makes it clear that you're storing 0.5 into the register half
that is used in other parts of the code below.

[Riku Voipio, 2015/11/02 12:24:12]

Ok, I'll define half = v0.2s, and halfs = v0.s to keep in line with rest of the
definitions (dX0 and dX0s for example). This will result a bit bigger patch.

 
 evenOddButterflyLoop:
 
 
         ld1     {dW0r},[argTwiddle],step1
         ld1     {dW1r},[argTwiddle], #8
 
         ld2     {dX0r,dX0i},[pSrc],step
         SUB     argTwiddle,argTwiddle,step1
         ld2     {dX1r,dX1i},[pSrc], #16
@@ skipping 84 matching lines @@
 
         st1     {dX0rs}[0],[argDst], #4
         fneg    dX0r,dX0r
         st1     {dX0rs}[1],[argDst], #4
 End:
 
         // Write function tail
         M_END
 
         .end